Example embodiments relate to methods of forming a trench in semiconductor devices. More particularly, example embodiments relate to methods of forming trenches having different depths in semiconductor devices.
Generally, non-volatile memory devices are capable of maintaining stored data without power. The non-volatile memory devices allow data to be electrically programmed therein or erased therefrom. The non-volatile memory devices are widely employed in various portable electronic devices such as MP3 players, cell phones, etc. for storing data.
The non-volatile memory devices may be divided according to a structure thereof into NAND-type memory devices and NOR-type memory devices. In the NAND-type memory devices, N unit cell transistors may be electrically connected to one another in series to form unit strings. The unit strings of the NAND-type memory devices may be electrically connected to one another in parallel between a bit line and a ground line. In the NOR-type memory devices, each of the cell transistors may be electrically connected to a bit line and a ground line in parallel.
The non-volatile memory devices may electrically control inputting/outputting of data utilizing a Fowler-Nordheim (F-N) tunneling mechanism or a channel hot electron injection mechanism. The non-volatile memory device utilizing the F-N tunneling mechanism may use a high voltage of tens of volts. The high voltage may cause a failure of the non-volatile memory devices due to breakdown voltages. In order to reduce or prevent the failure of the non-volatile memory devices, a trench in a peripheral region may be formed to be deeper and wider than a trench in a cell region.
Japanese Laid-Open Patent Publication No. 2006-080310, Japanese Laid-Open Patent Publication No. 2005-294759 and Japanese Laid-Open Patent Publication No. 11-195702 disclose methods of forming trenches having different depths in the cell region and the peripheral region, respectively. In these methods, a substrate is etched to form a cell trench having a narrow width in the cell region and a preliminary peripheral trench having a wide width in the peripheral region. The cell trench and the preliminary peripheral trench may have the same depth. An insulation layer is formed on the substrate to sufficiently fill up the cell trench. The insulation layer is conformally formed along profiles of an inner wall of the preliminary peripheral trench. The insulation layer is anisotropically etched to expose a lower face of the preliminary peripheral trench. The insulation layer remains on an inner sidewall of the preliminary peripheral trench. The exposed preliminary peripheral region trench is etched to form a peripheral trench that is deeper than the cell trench.
The peripheral trench formed using the above-mentioned method may have a stepped portion because the insulation layer remains in the inner sidewall. Thus, leakage current may be generated in the stepped portion.